The present invention relates to a semiconductor memory device, and more particularly, to a sense amplifier driving control circuit and method for controlling the discharge of a driving voltage of a circuit using an overdrive circuit. The sense amplifier driving control circuit discharges a core voltage used as the driving voltage.
A semiconductor memory device employs a sense amplifier to sense data and the sense amplifier is driven by a pull-up voltage and a pull-down voltage to perform a data sensing operation.
Referring to FIG. 1A, a pull-up voltage RTO and a pull-down voltage SB are supplied to a pull-up node and a pull-down node of a general sense amplifier, respectively. The sense amplifier detects a voltage difference between bit lines BL and /BL and amplifies that to a voltage difference between a core voltage VCORE and a ground voltage VSS by using the pull-up voltage RTO and the pull-down voltage SB.
That is, for the operation in the sense amplifier, the core voltage VCORE and the ground voltage VSS should be provided as the pull-up voltage RTO and the pull-down voltage SB, respectively. However, to improve tRCD performance by making the sense amplifier to sense relatively fast, the pull-up voltage RTO is provided with a supply voltage VDD during an overdrive period, which is a high pulse period of an overdrive control signal RTO1 as described in FIG. 1B.
Referring to FIG. 1B, as the overdrive control signal RTO1 transits to a low level and thus the overdrive period is terminated, at the same time thereof, a normal drive control signal RTO2 is enabled to a high level and then the pull-up voltage RTO provided to the sense amplifier is changed from the supply voltage VDD to the core voltage VCORE. At this time, a voltage level of the core voltage VCORE is raised by the inflow of a current due to the supply voltage VDD provided to the pull-up voltage RTO. Therefore, a circuit for recovering a voltage level of the core voltage VCORE that is raised by the supply voltage VDD to a target VCORE level is required. This circuit is called a core voltage (VCORE) discharge circuit.
FIG. 2 shows a phenomenon where the core voltage VCORE is raised by the overdrive. As the overdrive control signal RTO1 is disabled and the normal drive control signal RTO2 is enabled, the core voltage VCORE is raised by the supply voltage VDD provided to the pull-up voltage RTO and thus the core voltage VCORE becomes higher than the target voltage.
Therefore, if there is no VCORE discharge circuit, the voltage level of the core voltage VCORE starts to fall to its target voltage level slightly by a leakage phenomenon of a transistor or a small discharge transistor disposed in a core voltage driver for the stability of the voltage level of the core voltage VCORE. As such, it is difficult to maintain the target voltage level of the core voltage VCORE that is determined for an operation of a dynamic random access memory device (DRAM) and this could be a factor of inducing fail in the DRAM operation.
FIG. 3 illustrates a circuit diagram of a typical core voltage discharge circuit. Herein, a discharge control signal VCR_ON for controlling the discharge of the core voltage VCORE has a high value by being synchronized with a falling edge of the overdrive control signal RTO1. The core voltage discharge circuit operates during a period where the discharge control signal VCR_ON has the high value and in general the period has a time of about tens of nano seconds (ns).
In FIG. 3, a reference voltage VREFC is a reference voltage of the core voltage VCORE and generated from a reference voltage generator. Herein, it is assumed that the reference voltage VREFC has a voltage level of VCORE/2.
When the discharge control signal VCR_ON has a high level, a high level is coupled to a transistor N3 and thus a differential comparator including the transistor N3 is activated. The differential comparator compares the reference voltage VREFC with a voltage HFVCORE having a voltage level of VCORE/2 that is obtained by performing a voltage divide operation using two diode-connected transistors N9 and N10. If the voltage level of the core voltage VCORE is raised by the overdrive, the voltage HFVCORE has a higher voltage level than the reference voltage VREFC.
Thus, larger current flows through a transistor N2 and the potential of a node B becomes lower. This increases the drivability of a transistor P4 and thus the potential of a node DIS_N is raised. The raised voltage of the node DIS_N turns on a discharge transistor N7 and thus the core voltage VCORE is discharged.
FIG. 4 illustrates a typical circuit for generating the core voltage VCORE. In FIG. 4, the reference voltage VREFC is coupled to one input node of a comparator and the other input node of the comparator is connected to a node having a voltage level of VCORE/2 in a resistance divider of the core voltage VCORE, thereby allowing the core voltage VCORE to preserve a voltage level of 2 times of the stable voltage level of the reference voltage VREFC.
FIG. 5 is a view showing that the number of word lines WL is changed according to organizations of a semiconductor memory device. As illustrated in FIG. 5, in case of an X16 organization, a word line WL of a down bank and that of an up bank are generated at the same time. In the meantime, in case of X8 and X4 organizations, a word line WL of the up bank or that of the down bank is only generated according to row addresses.
When the semiconductor memory device operates in the X16 organization, a number of operating sense amplifiers is twice as large compared to that of the X4 or X8 organization. Thus, current of at least twice in magnitude compared to that of the X4 or X8 organization in response to the overdrive flows into the core voltage VCORE and the potential of the core voltage VCORE becomes higher than that in the case of the X4 or X8 organization.
On the other hand, when the semiconductor memory device operates in the X4 or X8 organization, relatively small current flows into the core voltage VCORE and thus the potential of the core voltage VCORE is only slightly raised as compared to the case of the X16 organization.
However, although the organization is changed, a discharge amount of the core voltage VCORE is not changed. If a discharge transistor for the core voltage VCORE is designed according to the X16 operation, the core voltage VCORE whose potential is raised by the overdrive is sufficiently discharged. But, in the X8 or X4 organization, although the sufficient discharge is performed in a discharge period, the discharge is continuously performed and opposes the core voltage drive. The opposition makes the voltage level of the core voltage VCORE to be lower than a target internal supply voltage level, so that a ringing phenomenon may occur. As a result, the current consumption also increases due to a current loss.
FIG. 6 is a view showing a side effect occurring when the discharge of the core voltage VCORE is constant while an amount of current due to the supply voltage VDD provided to the core voltage VCORE is changed according to the organizations.
This problem is one factor that induces a failure in the operation of a product employing X4, X8 and X16 organizations that are designed in one chip. This requires a size tuning of a discharge transistor and a discharge time tuning, resulting in the increase of development costs.
Although the tunings are performed, the problem is not perfectly solved and thus the core voltage level may become unstable. As a result, various functional deteriorations may occur. These kinds of failures are becoming much more serious when continuous read operations are performed.